Calyx implementation of AXI Interfaces

After successfully generating AXI-wrappers in Verilog, There was interest in showing that Calyx can help accelerate the development of interfaces and protocols generally. To that end, work was done on creating dynamically generated AXI-wrappers implemented in Calyx, as opposed to Verilog.

Creating this generator touched on a wide range of topics in the Calyx ecosystem. While the work performed can eventually be pieced together by me by going through the repos issues and PRs, a whirlwind tour of worked done to enable these generators follows:

• Create yxi, a memory interface schema to describe the shape of Calyx memories.
• Create a Cocotb testbench to verify correctness of AXI controllers.
• Create a handwritten AXI controller implemented in Calyx, hooked up to above testbench.
• Add fixes and features to our python builder.
• Create a dynamic AXI controller generator implemented in Calyx.
• Update Cargo build configurations.
• Introduce passes to the compiler.
• Introduce compiler driver build paths.
• (My favorite) introduce subtyping of components based on ports into Calyx.
• Introduce dynamic memory Calyx primitives with variable latencies to be used as stand ins to real, offchip memory.
• Introduce an AXI controller generator that removes latency assumptions regarding memories, working with dynamic memories introduced.
• Get our AXI controllers to integrate with XRT (Xilinx) via generated AXI-lite subordinate controllers
• My most recent contribution was to add a one-stop command to generate, execute, and verify the results of AXI-wrapped Calyx programs.

If you are interested in learning more about the AXI generator work I’ve contributed please visit this issue or reach out on the Calyx Zulip.