Dynamically Generated AXI Interfaces

Overview

I worked on a dynamic AXI generator in Rust that produced Verilog AXI wrappers that allows lowered Calyx programs (i.e RTL Verilog) to be simulated/executed on FPGAs. This work would not have been possible without the help of Rachit Nigam, Samuel Thomas, Andrew Butt, and Adrian Sampson.

Canonical AXI interfaces can be complex to implement correctly. So much so that even some of Xilinx’s (AMD’s FPGA division) own examples have bugs in their implementation that allow transactions to be lost.

AXI interfaces are required to interface with FPGA shells such as Xilinx’s XRT. While platforms like Vitis exist that nominally help with AXI generation, the implementations produced have historically been buggy, as mentioned above. Furthermore, relying on Vitis “wizards” is clunky and requires more buy-in to Vitis ecosystem than some would like.

This was the case at Capra. We had a desire to be able to run Calyx programs on FPGAs while being coupled to the Vitis ecosystem as little as possible. While we needed Vitis to be able to produce xclbins, we hoped to avoid opening up a GUI and invoking an “RTL Kernel Wizard”.

To enable easy execution, I worked on a dynamic AXI generator that took in Calyx programs as input, and output verilog files that contained both the lowered Calyx program as well as an AXI wrapper that allowed for our RTL design to interface with XRT.

This work was done in Rust, and built off of initial generators written by Samuel Thomas. Andrew Butt provided an immense amount of help in navigating AXI specs correctly, and debugging waveforms of buggy AXI interfaces. Without either of them, this work couldn’t have happened.